Full adder

ABSTRACT

A full adder composed essentially of six identical logic circuits each arranged to receive inputs A1, A2 . . . B1, B2... and to produce outputs C A1 + A2... + B1 + B2... and C A1 + A2... (B1 + B2...), the logic circuits being arranged to receive addend input values Xi and Yi and carry inputs Zi 1, and their complements, and being arranged in at least two groups of circuits, the first group producing an output carry signal and the second group receiving inputs from the first group and producing an output sum signal.

United States Patent 151 3,679,883 Straub 1 July 25, 1972 [54] FULL ADDER 3,566,098 2/1971 Kono ..23s 17s 3,548,182 12/1970 Pross 235/175 X [72] cmstame Germany 3,465,133 9/1969 Booher ..235/175 [73] Assignee: Telefunken Patentverwertungsgesellschaft, 3,454,751 7/1969 Brastins et aL. ...235/175 X Ulm/Danube, Germany 3,202,806 8/1965 Menne ..235/l68 X [22] Filed: 1970 Primary ExaminerEugene G. Botz [21 1 Appl. No.: 89,859 Assistant Examiner-James F. Gottman Attorney-Spencer & Kaye [30] Foreign Application Priority Data I 57 1 ABSTRACT 1969 Germany 19 57 302's A full adder composed essentially ofsix identical logic circuits each arranged to receive inputs Al, A2 B1, and to produce omputs C 2 Al A2", and C Tl i 235/168 73 175 A2... (B1 82...), the logic circuits being arranged to receive o arc addend input values X, and Y and carry inputs Z and their complements. and being arranged in at least two groups of cir- [56] References cued cuits, the first group producing an output carry signal and the UNITED STATES PATENTS second group receiving inputs from the first group and producing an output sum signal. 3,584,207 6/1971 Avsan et al. ..235/175 3,584,205 6/1971 Malaby et al. 235/175 X 8 Claims, 5 Drawing Figures W Xi Yi 7/ 5/2 2 822 A 2 52/ AZ/ CONNECT/N6 c/ 02 52- P NT A23 ,B/A A24 B25 Z/'-/ 5/3 B 523 AL? 71/4 A/5 L 3 L4 L 5 c5 53 c5 cs f /6 A26 Z C6 5/ T T 5/7 PATETEJUL 1912 3,679,883

lnvenfar. DieTer Srroub FULL ADDER BACKGROUND OF THE INVENTION The present invention relates to a full adder composed of a relatively small number of identical logic circuits.

The invention is directed to a full adder which forms the sum S X 6) Y) (Z, and the output carry 69 representing a modulo-2 addition, the logic'OR function and the logic AND function, the formation of the output carry requiring less time than the sum formation. Such full adders are known and permit rapid processing of carries passing through.

SUMMARY OF THE INVENTION It is the object of the present invention to construct an improved full adder with the use of logic circuits, particularly of the type disclosed in US. Pat. No. 3,504,192, issued to Herbert Stopper on Mar. 31st, I970, which have at least one first input (Al, A2,. and at least one second input (B1, B2,. and which link the input values fed to these inputs to form the following output values:

The present invention consists in that the addends X Y, and their complements Y are fed to a total of four inputs of a first group of logic circuits which form first output values X, Y 241+ Y X, Y X, Y that a second group of the logic circuits forms, from at least two of the first output values and from the input carry Z and its complement z; the output carry Z, and second output values; and that a logic circuit forms the sum S, from two of the second output values.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a is a block circuit diagram of a basic logic circuit employed in circuits according to the invention.

FIG. lb is a simplified symbolic representation of the circuit of FIG. la.

FIG. 2 is a schematic diagram, using the symbolic representation of FIG. lb, of one embodiment of a full adder according to the present invention.

FIG. 3 is a view similar to that of FIG. 2 of another embodiment of a full adder according to the present invention.

FIG. 4 is a schematic diagram of a practical embodiment of the logic circuit of FIG. la which is known, per se.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A logic circuiLwhicl links input values A and B into output values C A B and C A B, where the input value A can be replaced by the disjunctively linked values Al, A2 and the input value B can be replaced by the disjunctively linked values B1, B2 so that the previously mentioned linkage equations result, is disclosed in the above-mentioned U.S. Pat. No. 3,504,192. The logic circuit diagram of such a circuit having at least four inputs Al, A2, B1, B2 is shown in FIG. 1a. FIG. lb shows a simplified symbol for the circuit shown in FIG. la which will be used in illustrating circuits according to the invention.

In terms of logic function, the circuit of FIGS. la and 1b consists of two OR gates each receiving all of the A or B inputs and an ORNOT gate having its direct input connected to the A-input gate and its negated input connected to the B-input date. The ORNOT gate has a direct output C and a complementary output C. The logic circuit could also be considered as an OR gate receiving inputs A, a NOR gate receiving inputs B, and an OR gate receiving the outputs of the first two gates and having a direct function output and a complementary, or negated, function output.

FIG. 2 shows one stage of one preferred embodiment of the full adder according to the present invention. The index i indicates the bit location; a higher value of i corresponds to a higher bit location. The full adder of FIG. 2 contains seven logic circuits L1 to L7 each identical with the circuit of FIG. 1; however, only logic circuits L1 to L6 will initially be discussed below. The individual logic circuits each have four inputs Al, A2, B1, B2. The interconnection of the logic circuits and the association of input and output signal values with the inputs Alp A2p., B1 B2 where p,= l 6 and corresponds to the logic circuit reference numeral, and outputs Cp., CF is accomplished as follows:

Circuit Ll: All =x,; B11=Y Circuit L2: A12=XI; Bl2= Y,

For producing the above values it is assumed that the value fed to input A2 of logic circuit L6 i.e. input A26, is T= 0, where T is a clock pulse value and T is its complement, or inverte d value. The logic values appearing at outputs C1, C1, C2, C2 are represented by the abbreviated symbols P i, G G,, respectively.

The carry L requires less time for its information in this full adder than the sum S, inasmuch as the carry of the previous stage, or more exactly speaking its complement 2:, must pass through only one logic circuit before the carry Z, of the present stage is formed. At the output a the sum S, for the stage is available.

Since the full adder operates asynchronously, i.e. without the addition of a clock pulse, it will be advisable in many cases to provide a memory in which the value of sum S, can be stored. For this purpose a further logic circuit L7 is provided having its input A17 connected vith the output C6, its input B17 connected with its output C7, and its input B27 receiving a clock pulse signal T. At the same time, the inverted clock pulse signal T is fed to input A26 of logic circuit L6.

With this arrangement, signal S 'T is available at output C6. Upon the occurrence of a clock pulse T, this signal is transferred into the flipfiop formed by logic circuit L7, at whose output C7 it is available for the duration of the clock pulse and during the subsequent clock pulse interval. The connection of a circuit such as logic circuit L7 as such a flipflop is also disclosed in US. Pat. No. 3,504,192, at column 4, line 73, to column 5, line 2.

FIG. 3 shows another embodiment of the full adder according to the present invention which is constructed in a manner similar to that of the circuit of FIG. 2 of six logic circuits Ll to L6 and a logic circgitifl connected to act as a flipflop. Here, too, the values P,, P G G, are available at the outputs of the logic circuits Ll and L2. The interconnection of logic circuits L1 to L6 and the association of input values and output values As regards the speed of the carry formation and the transfer of sum S, into the memory fonned by logic circuit L7, the same applies as that stated with respect to the full adder of FIG. 2.

The logic circuits may be constructed in different ways. Advantageously the circuits are constructed in the manner disclosed in US. Pat. No. 3,504,192. One such circuit is illustrated herein in FIG. 4 and includes two transistors T1 and T2 which are connected in a current conducting manner with their emitters connected via a source of current I to one terminal of a voltage supply source providing a voltage -U and their collector resistors R1 connected to the other terminal of the voltage supply source. Connected in series with the control circuit of the one transistor T2 is a voltage source having a lower voltage than the voltage swing of the control signals applied to the transistors, i.e. the voltage swing between the logic values and l, the voltage provided by the series-connected voltage source preferably being one-half of such control signal voltage swing.

The voltage source which is connected in series with the control circuit of transistor T2 is represented in FIG. 4 by a resistor R2 and a current source circuit Q2 which produces a current of such an amplitude to flow through resistor R2 that the desired voltage drop is produced therein. The inputs of the circuit are Al, A2, B1 and B2 and the outputs of the circuit are C and 6. A more detailed description of this circuit can be found in US. Pat. No. 3,504,192, the circuit itself being illustrated in FIG. 8a of that patent.

A plurality or all of the logic circuits required for the construction of the full adder may be accommodated in a single integrated circuit. It is her: advantageous to bring one or a plurality of the values P P G a to individual connecting points where they can be tapped and are available for other logic connections.

The unused inputs of the logic circuit of FIGS. 2 and 3 are connected, depending on the circuit system employed, to a voltage corresponding to logic 0 or are left unconnected. The latter is possible in the circuit of FIG. 4 where the level corresponding to logic 1 is 0 volt and the level corresponding to logic 0 is a negative voltage.

It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

What is claimed is:

l. A binary full adder which forms the output sum 1 1 P t-i and the output carry from received values X, Z, Y 7,, Z and 2;, the formation of the output carry taking less time than the output sum formation, said adder comprising a plurality of logic circuits each having a plurality of first inputs A1, A2 a plurality of second inputs B1, 82..., a direct function output C and a corresponding negated function output and linkage means interconnecting said inputs and said outputs for establishing the relationships:

C=Al +A2... +31 +32...

( 3=Al +A2... -(B1 +B2...), wherein there is a first group of said logic circuits having a total of four of their said inputs connected to each to receive a respective one of the values X Y X. and Y: and arranged for producing at each of four of their said outputs gespective one of first output values X Y Yd T Y, Y, and X, Y

there is a second group of said logic circuits having inputs connected to two of said outputs of said first group and other inputs connected to receive the values 2 and 2: and arranged for producing the output carry L at the output of one of said logic circuits of said second group and a plurality of second output values which are functions of X Y, and Z at selected outputs of said logic circuits of said second group; and

a further one of said logic circuits has inputs connected to receive the second output values for producing the output sum S, at one of its outputs.

2. An arrangement as defined in claim 1 wherein said first and second groups of logic circuits and said further logic circuit consist of a total of not more than six of said logic circuits.

3. An arrangement as defined in claim 2 wherein said first and second groups and said further logic circuit consist of six logic circuits Lu, where p. is l, 2, 3, 4, 5 or 6 for each respective logic circuit, each of said logic circuits having two first inputs Aly. and AZu, two second inputs B1 and 82,41. and two outputs Cu. and (Ti, said inputs and outputs of said six logic circuits being connected as follows:

4. An arrangement as defined in claim 2 wherein said first and second groups and said further logic circuit consist of six logic circuits Lu, where ,u. is l, 2, 3, 4, 5, or 6 for each respective logic circuit, each said logic circuit having two first inputs Aly. and A2 two second inputs Blp. and 82p. and two outputs Cy. and CTL, said inputs and outputs of said six logic circuits being connected in the following manner:

which input no other signal is applied, is connected to receive a train of pulses constituting the complement of said clock pulses.

6. An arrangement as defined in claim 1 wherein each of said logic circuits comprises two transistors, the emitters of which are connected together and are also connected through a current supply circuit to the one pole of a voltage supply source and the collector resistors of which are connected to the other pole of said voltage supply source, and a voltage source connected in series with the control circuit of one said transistor, said voltage source producing a voltage which is lower than the voltage swing of the control signal supplied to said transistors.

7. An arrangement as defined in claim 1 wherein said adder is constructed according to integrated circuit techniques and at least several of said logic circuits are contained in a unitary integrated circuit.

8. An arrangement as defined in claim 1 further comprising at least one externally available connecting terminal to whichone of said four outputs of said first group of logic circuits is connected for permitting. its associated one of said first output values to be applied to an external circuit. 

1. A binary full adder which forms the output sum Si Xi + Yi + Zi 1 and the output carry Zi Xi . Yi + Xi . Zi 1 + Yi . Zi 1 from received values Xi, Xi, Yi, Yi, Zi 1 and Zi 1, the formation of the output carry taking less time than the output sum formation, said adder comprising a plurality of logic circuits each having a plurality of first inputs A1, A2 ..., a plurality of second inputs B1, B2..., a direct function output C and a corresponding negated function output C, and linkage means interconnecting said inputs and said outputs for establishing the relationships: C A1 + A2... + B1 + B2... C A1 + A2... . (B1 + B2...), wherein there is a first group of said logic circuits having a total of four of their said inputs connected to each to receive a respective one of the values Xi, Yi, Xi and Yi and arranged for producing at each of four of their said outputs a respective one of first output values Xi + Yi, Xi + Yi, Xi . Yi and Xi . Yi; there is a second group of said logic circuits having inputs connected to two of said outputs of said first group and other inputs connected to receive the values Zi 1 and Zi 1 and arranged for producing the output carry Zi at the output of one of said logic circuits of said second group and a plurality of second output values which are functions of Xi, Yi and Zi 1 at selected outputs of said logic circuits of said second group; and a further one of said logic circuits has inputs connected to receive the second output values for producing the output sum Si at one of its outputs.
 2. An arrangement as defined in claim 1 wherein said first and second groups of logic circuits and said further logic circuit consist of a total of not more than six of said logic circuits.
 3. An arrangement as defined in claim 2 wherein said first and second groups and said further logic circuit consist of six logic circuits L Mu , where Mu is 1, 2, 3, 4, 5 or 6 for each respective logic circuit, each of said logic circuits having two first inputs A1 Mu and A2 Mu , two second inputs B1 Mu and B2 Mu and two outputs C Mu and C Mu , said inputs and outputs of said six logic circuits being connected as follows:
 4. An arrangemEnt as defined in claim 2 wherein said first and second groups and said further logic circuit consist of six logic circuits L Mu , where Mu is 1, 2, 3, 4, 5, or 6 for each respective logic circuit, each said logic circuit having two first inputs A1 Mu and A2 Mu , two second inputs B1 Mu and B2 Mu and two outputs C Mu and C Mu , said inputs and outputs of said six logic circuits being connected in the following manner:
 5. An arrangement as defined in claim 1 wherein there is an additional one of said logic circuits having one of its inputs connected to that one of said outputs of said further logic circuit providing the output sum Si, said output C of said additional logic circuit being connected to one of said second inputs of said additional logic circuit, another second input of said additional logic circuit being connected to receive a train of clock pulses, and a first input of said further logic circuit, to which input no other signal is applied, is connected to receive a train of pulses constituting the complement of said clock pulses.
 6. An arrangement as defined in claim 1 wherein each of said logic circuits comprises two transistors, the emitters of which are connected together and are also connected through a current supply circuit to the one pole of a voltage supply source and the collector resistors of which are connected to the other pole of said voltage supply source, and a voltage source connected in series with the control circuit of one said transistor, said voltage source producing a voltage which is lower than the voltage swing of the control signal supplied to said transistors.
 7. An arrangement as defined in claim 1 wherein said adder is constructed according to integrated circuit techniques and at least several of said logic circuits are contained in a unitary integrated circuit.
 8. An arrangement as defined in claim 1 further comprising at least one externally available connecting terminal to which one of said four outputs of said first group of logic circuits is connected for permitting its associated one of said first output values to be applied to an external circuit. 